The present invention relates to a pulse generation circuit applied to generation etc. of a pulse of a clock in a circuit such as an LSI.
FIGS. 18 through 21 are diagrams each showing an example of a conventional pulse generation circuit. The pulse generation circuit shown in FIG. 18 is constructed of a 2-input NAND circuit 11, a delay circuit 12 consisting of inverters provided at odd-numbered stages, and an inverter 13. When an input pulse signal (positive pulse) is inputted to this pulse generation circuit, this pulse is inputted to one input of the NAND circuit 11, and a negative pulse with a predetermined delay is inputted to the other input of the NAND circuit 11 via the delay circuit 12. Accordingly, an output of the NAND circuit 11 is kept at a Lo-level during a period from a rise of the pulse signal inputted from an input line CLK down to a fall of the output pulse of the delay circuit 12, and hence the inverter 13 inverts this pulse, thereby generating a pulse clk. Namely, this pulse generation circuit functions as a so-called chopper that sets the input pulse signal to a pulse width corresponding an amount of the delay.
Further, the pulse generation circuit shown in FIG. 19 is constructed of a 2-input NOR circuit 14, a delay circuit 16 consisting of inverters provided at even-numbered stages, and an inverter 13. When an input pulse signal CLK is inputted to this pulse generation circuit, this pulse is inputted to one input of the NOR circuit 14, and a pulse with a predetermined delay is inputted to the other input of the NOR circuit 14 via the delay circuit 16. Accordingly, an output of the NOR circuit 14 is kept at the Lo-level during a period from a rise of the input pulse signal down to a fall of the output pulse of the delay circuit 16, so that the inverter 13 inverts this, thereby generating a pulse. Namely, this pulse generation circuit functions as a so-called extender that elongates (extends) a pulse width of the input pulse signal by an amount of the delay.
Without being limited to these static type pulse generation circuits, as shown in FIG. 20, there is also proposed a dynamic type pulse generation circuit, wherein a keeper 15 keeps a level from a rise of the input pulse signal CLK to a rise of an output pulse of a delay circuit 21, thus generating a pulse.
Moreover, the pulse generation circuit shown in FIG. 21 includes a feedback circuit, wherein an output signal is fed back and used for resetting or terminating the pulse (refer to Patent document 1).
[Patent Document 1]
Japanese Patent Application Laid-Open Publication No. 2000-188528
[Patent Document 2]
Japanese Patent Application Laid-Open Publication No. 11-136098